1. Field of the Invention
The invention relates to a driving circuit system and a method of elevating a slew rate and. More particularly, the invention relates to a driving circuit system having an operational amplifier (op-amp) with a high slew rate and a method of elevating a slew rate of an operational amplifier.
2. Description of the Prior Art
The operational amplifier structure has a lot of application in modern electronic appliance. For example, the amplifying circuit used in signal processing, the driving circuit used in driving a capacitive load and the signal converting circuit used in converting signals between analog and digital are both practical implements with the operational amplifier structure. Especially, the liquid crystal display (LCD) monitor must drive a great deal of pixel capacitors to compose the displaying image, so that the operational amplifier is usually adopted in a driving circuit.
With the LCD displaying technology developing, the LCD monitor is heading to have a higher display resolution, a larger size and a rapider response time, therefore, there are more challenges in design the driving circuit. The source driver circuit in the LCD monitor includes an output buffer. The output buffer is used for controlling the transmitting of the video information according to a control signal (usually the STB signal).
Please refer to FIG. 1. FIG. 1 is a schematic diagram illustrating a driving circuit system 1 in prior art. The driving circuit system 1 can serves as an output buffer of a source driver circuit. As shown in FIG. 1, the driving circuit system 1 includes an operational amplifier 10, a feedback loop cooperating with the operational amplifier 10 and an output switch 12, such that the operational amplifier 10 may function as the output buffer. The operational amplifier 10 is biased by a bias current Ibias. An output terminal of the operational amplifier 10 is coupled to the output switch 12. The output switch 12 is controlled by a control signal C, which can be a STB signal in practical application. The output switch 12 cooperates with the operational amplifier 10 to switch between the states of registering an input signal Sin or generating an output signal Sout.
In practical application, to boost the gray level performance of the video display, it needs the operational amplifier to have a full range of input swing, or in other words, a rail-to-rail input range. Therefore, the operational amplifier with a rail-to-rail input stage is widely adopted. Please refer to FIG. 2. FIG. 2 is a circuit pattern diagram illustrating the operational amplifier 10 in the prior art. As shown in FIG. 2, the operational amplifier 10 in practical application may have a parallel rail-to-rail input stage 100 and a class AB output stage.
In general, when the voltage output signal of the output buffer is switched, the changing of the voltage output signal is not ideal but has a certain delay. It takes a certain settling time to complete the changing.
Please refer to FIG. 3. FIG. 3 is a timing diagram illustrating an output voltage of the driving circuit system 1 of prior art. As shown in FIG. 3, at the beginning, the output voltage may approach to the high level or the low level according the last display state. There is an example illustrating the output voltage changing from the low level to the high level to the demand for displaying. When the operational amplifier received the control signal C at time spot T1, the input voltage started to change from the low level to the high level. Till the output voltage exceeds the high level threshold voltage Vh at the time spot T2, the output voltage has completed the switching operation. The output voltage will approach to and eventually be stable at the high level.
The time period between time spot T1 and the time spot T2 is the mentioned settling time Ts, which is the time period of the output voltage from triggered by the negative edge trigger of the control signal C till exceeding the high level threshold voltage Vh.
On the other hand, the output voltage may need to change from the high level to the low level to the demand for displaying. It takes a settling time Ts from starting changing till descending across the low level threshold voltage VL. The detail manner is similar to said description above.
That is to say, while the source driver circuit is generating the voltage output signal, the settling time Ts is needs for the LCD monitor to complete its function, such that the response speed is limited.
The higher is the slew rate of the operational amplifier within the output buffer, the shorter the settling time is. Consequently, the driving response speed of the source driver circuit is accelerated, and therefore the LCD monitor has a better response time behavior. In prior art, it may elevate the slew rate of the operational amplifier in ways of:
a) reducing the capacitance of a compensation capacitor
By reducing the capacitance of the compensation capacitor, it reduces the charging time can be reduced, and further accelerates the response time and elevates the slew rate of the operational amplifier. However, it reduces the stability of the operational amplifier.
b) adopting a push-pull output stage
Utilizing a differential amplifier for pushing the output stage to form a push-pull output stage can elevate the slew rate of the operational amplifier as well. However, the extra differential amplifier circuit may complex the driving circuit, and further to enlarge the die size of the driving circuit and the static current consumption.
On the other hand, in order to drive a great deal of pixel loads, the present source driver circuit must have a lots of the driving circuit (such as said driving circuit system 1) for corresponding the pixel loads, and it results in a heavy consumption of electricity. Therefore, the source driver circuit in practical application usually includes a charge sharing circuit structure. Please refer to FIG. 4 and FIG. 5 as well. FIG. 4 is a schematic diagram illustrating a driving circuit system 2a and a driving circuit system 2b in prior art. FIG. 5 is a timing diagram illustrating the relation between the output voltage of the operational amplifier 20 in FIG. 4 and the control signal under charge sharing condition. As shown in FIG. 4, each driving circuit system includes an operational amplifier 20, feedback loop cooperating with the operational amplifier 20, an output switch 22 and another output switch 24. There are two sets of the driving circuit systems (2a, 2b) shown in FIG. 4 for explanation, however the total number of sets of the driving circuit systems should correspond to the total number of the pixel capacitor to be driven.
Compared with said driving circuit system, the biggest difference of the driving circuit system in FIG. 4 is to include the output switches 24 controlled by the charge sharing signal CS, so as to form the charge sharing circuit structure.
As shown in FIG. 5, the charge sharing signal may control the output switches 24 to join output voltages at different voltage levels. For example, originally the output voltage of the driving circuit system 2a locates at the high level and the output voltage of the driving circuit system 2b locates at the low level. When the charge sharing signal CS turns on the output switches 24, the output voltages are adjusted to an intermediate level in a way of shorting and averaging two output voltages. It does not need extra power supply such that the power consumption can be reduced.
However, the driving circuit system with charge sharing structure would generate an output voltage noise (as the noise N shown in FIG. 5) at the negative edge of the control signal C (usually the STB signal in practical usage). The noise decreases the stability of the driving circuit system.
Therefore, the invention discloses a driving circuit system and a method capable of elevating a slew rate of an operational amplifier, so as to solve said problems.